CIS structure with complementary metal grid and deep trench isolation and method for manufacturing the same

ABSTRACT

A CMOS image sensor structure includes a substrate and pixel portions. Each pixel portion includes intersection areas, the border areas each of which is located between any two adjacent ones of the intersection areas, and a central area surrounded by the intersection areas and the border areas. Each pixel portion includes a device layer, an anti-reflective coating layer, discrete reflective structures, discrete metal blocking structures, a passivation layer and a color filter. The device layer is disposed on the substrate. Trenches are formed in the device layer and the substrate corresponding to the border areas respectively. The anti-reflective coating layer conformally covers the device layer, the substrate and the trenches. The reflective structures are disposed in the trenches. The metal blocking structures overly the anti-reflective coating layer in the intersection areas. The passivation layer conformally covers the metal blocking structures. The color filter is disposed on the passivation layer.

PRIORITY CLAIM AND CROSS-REFERENCE

This is a divisional application of U.S. patent application Ser. No.14/925,576 filed on Oct. 28, 2015, which is incorporated herein byreference in its entirety.

BACKGROUND

Semiconductor image sensors are operated to sense light. Typically, thesemiconductor image sensors include complementarymetal-oxide-semiconductor (CMOS) image sensors (CIS) and charge-coupleddevice (CCD) sensors, which are widely used in various applications suchas digital still camera (DSC), mobile phone camera, digital video (DV)and digital video recorder (DVR) applications. These semiconductor imagesensors utilize an array of image sensor elements, each image sensorelement including a photodiode and other elements, to absorb light andconvert the sensed light into digital data or electrical signals.

A front side illuminated (FSI) CMOS image sensor and a back sideilluminated (BSI) CMOS image sensor are two types of CMOS image sensors.The FSI CMOS image sensor is operable to detect light projected from itsfront side while the BSI CMOS image sensor is operable to detect lightprojected from its backside. The BSI CMOS image sensor can shortenoptical paths and increase fill factors to improve light sensitivity perunit area and quantum efficiency, and can reduce cross talk and photoresponse non-uniformity. Hence, the image quality of the CMOS imagesensor can be significantly improved. Furthermore, the BSI CMOS imagesensor has a high chief ray angle, which allows a shorter lens height tobe implemented, so that a thinner camera module is achieved.Accordingly, the BSI CMOS image sensor technology is becoming amainstream technology.

However, conventional BSI CMOS image sensors and methods of fabricatingthe BSI CMOS image sensors have not been entirely satisfactory in everyaspect.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIG. 1A is a schematic view of a layout of a metal grid structure of aCMOS image sensor structure in accordance with various embodiments.

FIG. 1B is a schematic view of a layout of reflective structures of aCMOS image sensor structure in accordance with various embodiments.

FIG. 1C is schematic cross-sectional view of the CMOS image sensorstructure taken along line A-A of FIG. 1A and FIG. 1B.

FIG. 1D is schematic cross-sectional view of the CMOS image sensorstructure taken along line B-B of FIG. 1A and FIG. 1B.

FIG. 1E is schematic cross-sectional view of the CMOS image sensorstructure taken along line C-C of FIG. 1A and FIG. 1B.

FIG. 2A is a schematic view of a layout of a metal grid structure of aCMOS image sensor structure in accordance with various embodiments.

FIG. 2B is a schematic view of a layout of reflective structures of aCMOS image sensor structure in accordance with various embodiments.

FIG. 2C is schematic cross-sectional view of the CMOS image sensorstructure taken along line A-A of FIG. 2A and FIG. 2B.

FIG. 2D is schematic cross-sectional view of the CMOS image sensorstructure taken along line B-B of FIG. 2A and FIG. 2B.

FIG. 2E is schematic cross-sectional view of the CMOS image sensorstructure taken along line C-C of FIG. 2A and FIG. 2B.

FIG. 3A through FIG. 3I are schematic cross-sectional views ofintermediate stages showing a method for manufacturing a CMOS imagesensor structure in accordance with various embodiments.

FIG. 4 is a flow chart of a method for manufacturing a CMOS image sensorstructure in accordance with various embodiments.

FIG. 5A through FIG. 5I are schematic cross-sectional views ofintermediate stages showing a method for manufacturing a CMOS imagesensor structure in accordance with various embodiments.

FIG. 6 is a flow chart of a method for manufacturing a CMOS image sensorstructure in accordance with various embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components and arrangements are describedbelow to simplify the present disclosure. These are, of course, merelyexamples and are not intended to be limiting. For example, the formationof a first feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact.

Terms used herein are only used to describe the specific embodiments,which are not used to limit the claims appended herewith. For example,unless limited otherwise, the term “one” or “the” of the single form mayalso represent the plural form. The terms such as “first” and “second”are used for describing various devices, areas and layers, etc., thoughsuch terms are only used for distinguishing one device, one area or onelayer from another device, another area or another layer. Therefore, thefirst area can also be referred to as the second area without departingfrom the spirit of the claimed subject matter, and the others arededuced by analogy. In addition, the present disclosure may repeatreference numerals and/or letters in the various examples. Thisrepetition is for the purpose of simplicity and clarity and does not initself dictate a relationship between the various embodiments and/orconfigurations discussed. As used herein, the term “and/or” includes anyand all combinations of one or more of the associated listed items.

In a typical CMOS image sensor, a trench isolation layer, which isformed in a device layer and a substrate underlying the device layer,and a metal grid layer formed on the trench isolation layer are used toform a light guide structure to constrain an incident light, so as toprevent crosstalk. However, the metal grid layer inevitably blocks theincident light, such that quantum efficiency (QE) of the CMOS imagesensor is lowered. In addition, the operation of forming the trenchisolation layer includes using a dry etching process to form a trench inthe device layer and the substrate, and depositing a reflective materialto fill the trench. However, the dry etching process damages a bottomand a side surface of the trench, thus an imaging performance of theCMOS image sensor is degraded.

Embodiments of the present disclosure are directed to providing a CMOSimage sensor structure and a method for manufacturing the CMOS imagesensor structure, in which a layout of a metal grid structure overlyinga device layer and a layout of reflective structures are complementary,such that a light guide mechanism of the metal grid structure and thereflective structures is kept for corsstalk improvement while the metalgrid structure and the reflective structures release some areas foroptical performance improvement. Furthermore, an occupied area of themetal grid structure is decreased, thus increasing quantum efficiency ofthe CMOS image sensor structure. Moreover, an occupied area of thereflective structures is decreased, such that damage of the device layerand the substrate caused during the formation of the reflectivestructures is reduced, thereby enhancing an imaging performance of theCMOS image sensor and enlarging a process window.

Referring to FIG. 1A and FIG. 1B, FIG. 1A is a schematic view of alayout of a metal grid structure of a CMOS image sensor structure inaccordance with various embodiments, and FIG. 1B is a schematic view ofa layout of reflective structures of a CMOS image sensor structure inaccordance with various embodiments. A layout 100 of a metal gridstructure 102 and a layout 104 of reflective structures 106 in a CMOSimage sensor structure 120 (referring to FIG. 1C) are mesh-like layouts,in which each of the layouts 100 and 104 is modified by removing someportions from a mesh layout. The metal grid structure 102 includesvarious metal blocking structures 116. As shown in FIG. 1A and FIG. 1B,the metal grid structure 102 and the reflective structures 106collectively define various pixel portions 108. The pixel portions 108are arranged in an array, and are adjacent to each other. The metal gridstructure 102 and the reflective structures 106 are configured toprevent the light from diffusing to the adjacent pixel portions 108.

In some examples, each of the pixel portions 108 includes variousintersection areas 110, various border areas 112 and a central area 114.As shown in FIG. 1A and FIG. 1B, the intersection areas 110 arerespectively located at corners of the pixel portion 108. The borderareas 112 are respectively located at borders of the pixel portion 108,and each of the border areas 112 is located between any two adjacentones of the intersection areas 110. The central area 114 is located at acenter of the pixel portion 108 and is surrounded by the intersectionareas 110 and the border areas 112. The metal blocking structures 116 ofthe metal grid structure 102 and the reflective structures 106 arearranged in a complementary manner. In the embodiment, the metalblocking structures 116 are respectively disposed in the intersectionareas 110, and the reflective structures 106 are respectively disposedin the border areas 112. In some examples, adjacent ones of the metalblocking structures 116 in the intersection areas 110 which are adjacentto each other are combined to form a shape of a crisscross.

Referring to FIG. 1C, FIG. 1D and FIG. 1E, FIG. 1C is schematiccross-sectional view of the CMOS image sensor structure taken along lineA-A of FIG. 1A and FIG. 1B, FIG. 1D is schematic cross-sectional view ofthe CMOS image sensor structure taken along line B-B of FIG. 1A and FIG.1B, and FIG. 1E is schematic cross-sectional view of the CMOS imagesensor structure taken along line C-C of FIG. 1A and FIG. 1B. The CMOSimage sensor structure 120 may be operated for sensing incident light122. The CMOS image sensor structure 120 has a front side 124 and a backside 126. In some examples, the CMOS image sensor structure 120 is a BSICMOS image sensor device, which is operated to sense the incident light122 projected from its back side 126.

As shown in FIG. 1C, FIG. 1D and FIG. 1E, the CMOS image sensorstructure 120 includes a substrate 128 and the pixel portions 108. Thesubstrate 128 is a semiconductor substrate, and may be composed of asingle-crystalline semiconductor material or a compound semiconductormaterial. For example, silicon, germanium or glass may be used as amaterial of the substrate 128.

The pixel portions 108 are arranged on the substrate 128 in an array andare adjacent to each other. In some examples, as shown in FIG. 1C, FIG.1D and FIG. 1E, each of the pixel portions 108 includes a device layer130, an anti-reflective coating layer 132, various discrete reflectivestructures 106, various discrete metal blocking structures 116, apassivation layer 134 and a color filter 136.

In each of the pixel portions 108, the device layer 130 is disposed inthe intersection areas 110, the border areas 112 and the central area114 on the substrate 128. In some examples, a material of the devicelayer 130 includes silicon. For example, the material of the devicelayer 130 may include epitaxial silicon. Referring to FIG. 1C and FIG.1E again, various trenches 138 are formed in the device layer 130 andthe substrate 128 corresponding to the border areas 112 respectively.Each of the trenches 138 extends from a top of the device layer 130 tothe substrate 128. In some examples, each of the trenches 138 is a deeptrench.

As shown in FIG. 1C, FIG. 1D and FIG. 1E, the anti-reflective coatinglayer 132 conformally covers the device layer 130, the substrate 128 andthe trenches 138. The anti-reflective coating layer 132 is configured toprevent the light from diffusing to the adjacent pixel portions 108. Forexample, the anti-reflective coating layer 132 may be formed fromsilicon oxide.

The reflective structures 106 are disposed on the anti-reflectivecoating layer 132 and fill the trenches 138 respectively. The reflectivestructures 106 may be formed from metal or dielectric material. In someexemplary examples, the reflective structures 106 are formed from thedielectric material, and each of the reflective structures 106 is a deeptrench isolation (DTI) structure. For example, each of the reflectivestructures 106 may have a height ranging from about 0.1 micrometer toabout 2.5 micrometer. The trenches 138 are formed in the border areas112, such that the reflective structures 106 filling in the trenches 138are located in the border areas 112.

In some examples, as shown in FIG. 1E, the CMOS image sensor structure120 may optionally include a buffer layer 140. The buffer layer 140 isdisposed on the anti-reflective coating layer 132 and the reflectivestructures 106, and is located between the anti-reflective coating layer132 and the metal grid structure 102 and between the anti-reflectivecoating layer 132 and the passivation layer 134. The buffer layer 140 issuitable for use in increasing the adhesion between the metal gridstructure 102 and the anti-reflective coating layer 132. For example,the buffer layer 140 may be formed from a dielectric layer, such assilicon dioxide.

The metal grid structure 102 is disposed on the buffer layer 140, andoverlies the anti-reflective coating layer 132. The metal blockingstructures 116 of the metal grid structure 102 are disposed in theintersection areas 110 respectively. In the embodiment, as shown in FIG.1E, the metal blocking structures 116 are disposed in the intersectionareas 110 while the reflective structures 106 are disposed in the borderareas 112, such that the metal blocking structures 116 and thereflective structures 106 are staggered and arranged in a complementarymanner in each of the pixel portions 108. In some examples, the metalblocking structures 116 are formed from metal or a metal alloy, such astungsten or an aluminum-copper alloy. The metal blocking structures 116and the reflective structures 106 may be formed from the same material,or may be formed from different materials.

Referring to FIG. 1E again, the passivation layer 134 conformally coversthe metal blocking structures 116 and the buffer layer 140 whichoverlies the anti-reflective coating layer 132 and the reflectivestructures 106. The passivation layer 134 is suitable for use inprotecting the metal blocking structures 116 from being corroded by thecolor filters 136. In some examples, the passivation layer 134 is formedfrom silicon oxide, silicon nitride or silicon oxynitride.

As shown in FIG. 1C, FIG. 1D and FIG. 1E, the color filter 136 isdisposed on the passivation layer 134 in the intersection areas 110, theborder areas 112 and the central area 114. In some exemplary examples,the color filter 136 is a red color filter, a blue color filter or agreen color filter. In some examples, a top surface 142 of the colorfilter 136 is higher than a top 144 of the passivation layer 134. Insome examples, each of the pixel portions 108 may optionally include amicro lens 146. The micro lens 146 covers the top surface 142 of thecolor filter 136.

In each of the pixel portions 108, the layout 100 of the metal gridstructure 102 and the layout 104 of the reflective structures 106 arecomplementary, such that a light guide mechanism of the metal gridstructure and the reflective structures is kept for corsstalkimprovement while the metal grid structure 102 and the reflectivestructures 106 can release some areas for optical performanceimprovement. Furthermore, an occupied area of the metal grid structure102 is decreased, such that quantum efficiency of the CMOS image sensorstructure 120 is increased. Moreover, an occupied area of the reflectivestructures 106 is decreased, such that damage of the device layer 130and the substrate 128 caused during the dry etching process of thetrenches 138 is reduced, thereby enhancing an imaging performance of theCMOS image sensor 120 and enlarging a process window.

Referring to FIG. 2A and FIG. 2B, FIG. 2A is a schematic view of alayout of a metal grid structure of a CMOS image sensor structure inaccordance with various embodiments, and FIG. 2B is a schematic view ofa layout of reflective structures of a CMOS image sensor structure inaccordance with various embodiments. A layout 200 of a metal gridstructure 202 and a layout 204 of reflective structures 206 in a CMOSimage sensor structure 220 (referring to FIG. 2C) are mesh-like layouts,in which each of the layouts 200 and 204 is modified by removing someportions from a mesh layout. The metal grid structure 202 includesvarious metal blocking structures 216. As shown in FIG. 2A and FIG. 2B,the metal grid structure 202 and the reflective structures 206collectively define various pixel portions 208. The pixel portions 208are arranged in an array, and are adjacent to each other. The metal gridstructure 202 and the reflective structures 206 are configured toprevent the light from diffusing to the adjacent pixel portions 208.

In some examples, each of the pixel portions 208 includes variousintersection areas 210, various border areas 212 and a central area 214.As shown in FIG. 2A and FIG. 2B, the intersection areas 210 arerespectively located at corners of the pixel portion 208. The borderareas 212 are respectively located at borders of the pixel portion 208,and each of the border areas 212 is located between any two adjacentones of the intersection areas 210. The central area 214 is located at acenter of the pixel portion 208 and is surrounded by the intersectionareas 210 and the border areas 212. The metal blocking structures 216 ofthe metal grid structure 202 and the reflective structures 206 arearranged in a complementary manner. In the embodiment, the metalblocking structures 216 are respectively disposed in the border areas212, and the reflective structures 206 are respectively disposed in theintersection areas 210. In some examples, adjacent ones of thereflective structures 206 in the intersection areas 210 which areadjacent to each other are combined to form a shape of a crisscross.

Referring to FIG. 2C, FIG. 2D and FIG. 2E, FIG. 2C is schematiccross-sectional view of the CMOS image sensor structure taken along lineA-A of FIG. 2A and FIG. 2B, FIG. 2D is schematic cross-sectional view ofthe CMOS image sensor structure taken along line B-B of FIG. 2A and FIG.2B, and FIG. 2E is schematic cross-sectional view of the CMOS imagesensor structure taken along line C-C of FIG. 2A and FIG. 2B. The CMOSimage sensor structure 220 may be operated for sensing incident light222. The CMOS image sensor structure 220 has a front side 224 and a backside 226. In some examples, the CMOS image sensor structure 220 is a BSICMOS image sensor device, which is operated to sense the incident light222 projected from its back side 226.

As shown in FIG. 2C, FIG. 2D and FIG. 2E, the CMOS image sensorstructure 220 includes a substrate 228 and the pixel portions 208. Thesubstrate 228 is a semiconductor substrate, and may be composed of asingle-crystalline semiconductor material or a compound semiconductormaterial. For example, silicon, germanium or glass may be used as amaterial of the substrate 228.

The pixel portions 208 are arranged on the substrate 228 in an array andare adjacent to each other. In some examples, as shown in FIG. 2C, FIG.2D and FIG. 2E, each of the pixel portions 208 includes a device layer230, an anti-reflective coating layer 232, various discrete reflectivestructures 206, various discrete metal blocking structures 216, apassivation layer 234 and a color filter 236.

In each of the pixel portions 208, the device layer 230 is disposed inthe intersection areas 210, the border areas 212 and the central area214 on the substrate 228. In some examples, a material of the devicelayer 230 includes silicon. For example, the material of the devicelayer 230 may include epitaxial silicon. Referring to FIG. 2C and FIG.2D again, various trenches 238 are formed in the device layer 230 andthe substrate 228 corresponding to the intersection areas 210respectively. Each of the trenches 238 extends from a top of the devicelayer 230 to the substrate 228. In some examples, each of the trenches238 is a deep trench.

As shown in FIG. 2C, FIG. 2D and FIG. 2E, the anti-reflective coatinglayer 232 conformally covers the device layer 230, the substrate 228 andthe trenches 238. The anti-reflective coating layer 232 is configured toprevent the light from diffusing to the adjacent pixel portions 208. Forexample, the anti-reflective coating layer 232 may be formed fromsilicon oxide.

The reflective structures 206 are disposed on the anti-reflectivecoating layer 232 and fill the trenches 238 respectively. The reflectivestructures 206 may be formed from metal or dielectric material. In someexemplary examples, the reflective structures 206 are formed from thedielectric material, and each of the reflective structures 206 is a deeptrench isolation structure. For example, each of the reflectivestructures 206 may have a height ranging from about 0.1 micrometer toabout 2.5 micrometer. The trenches 238 are formed in the intersectionareas 210, such that the reflective structures 206 filling in thetrenches 238 are located in the intersection areas 210.

In some examples, as shown in FIG. 2E, the CMOS image sensor structure220 may optionally include a buffer layer 240. The buffer layer 240 isdisposed on the anti-reflective coating layer 232 and the reflectivestructures 206, and is located between the anti-reflective coating layer232 and the metal grid structure 202 and between the anti-reflectivecoating layer 232 and the passivation layer 234. The buffer layer 240 issuitable for use in increasing the adhesion between the metal gridstructure 202 and the anti-reflective coating layer 232. For example,the buffer layer 240 may be formed from a dielectric layer, such assilicon dioxide.

The metal grid structure 202 is disposed on the buffer layer 240, andoverlies the anti-reflective coating layer 232. The metal blockingstructures 216 of the metal grid structure 202 are disposed in theborder areas 212 respectively. In the embodiment, as shown in FIG. 2E,the metal blocking structures 216 are disposed in the border areas 212while the reflective structures 206 are disposed in the border areas210, such that the metal blocking structures 216 and the reflectivestructures 206 are staggered and arranged in a complementary manner ineach of the pixel portions 208. In some examples, the metal blockingstructures 216 are formed from metal or a metal alloy, such as tungstenor an aluminum-copper alloy. The metal blocking structures 216 and thereflective structures 206 may be formed from the same material, or maybe formed from different materials.

Referring to FIG. 2E again, the passivation layer 234 conformally coversthe metal blocking structures 216 and the buffer layer 240 whichoverlies the anti-reflective coating layer 232 and the reflectivestructures 206. The passivation layer 234 is suitable for use inprotecting the metal blocking structures 216 from being corroded by thecolor filters 236. In some examples, the passivation layer 234 is formedfrom silicon oxide, silicon nitride or silicon oxynitride.

As shown in FIG. 2C, FIG. 2D and FIG. 2E, the color filter 236 isdisposed on the passivation layer 234 in the intersection areas 210, theborder areas 212 and the central area 214. In some exemplary examples,the color filter 236 is a red color filter, a blue color filter or agreen color filter. In some examples, a top surface 242 of the colorfilter 236 is higher than a top 244 of the passivation layer 234. Insome examples, each of the pixel portions 208 may optionally include amicro lens 246. The micro lens 246 covers the top surface 242 of thecolor filter 236.

In each of the pixel portions 208, the layout 200 of the metal gridstructure 202 and the layout 204 of the reflective structures 206 arecomplementary, such that a light guide mechanism of the metal gridstructure and the reflective structures is kept for corsstalkimprovement while the metal grid structure 202 and the reflectivestructures 206 can release some areas for optical performanceimprovement. Furthermore, an occupied area of the metal grid structure202 is decreased, such that quantum efficiency of the CMOS image sensorstructure 220 is increased. Moreover, an occupied area of the reflectivestructures 206 is decreased, such that damage of the device layer 230and the substrate 228 caused during the dry etching process of thetrenches 238 is reduced, thereby enhancing an imaging performance of theCMOS image sensor 220 and enlarging a process window.

FIG. 3A through FIG. 3I are schematic cross-sectional views ofintermediate stages showing a method for manufacturing a CMOS imagesensor structure in accordance with various embodiments. As shown inFIG. 3A, a substrate 300 is provided. The substrate 300 is asemiconductor substrate, and may be composed of a single-crystallinesemiconductor material or a compound semiconductor material. Forexample, silicon, germanium or glass may be used as a material of thesubstrate 300.

Referring to FIG. 3A again, a device layer 302 is formed on thesubstrate 300 by using, for example, a deposition technique, anepitaxial technique or a bonding technique. In some examples, theoperation of forming the device layer 302 includes forming the devicelayer 302 from silicon. For example, the device layer 302 may be formedfrom epitaxial silicon.

As shown in FIG. 3B, various trenches 304 are formed in the device layer302 and the substrate 300. In the embodiment, the trenches 304 are onlyformed in border areas 306. In some examples, the operation of formingthe trenches 304 is performed to form various deep trenches. Theoperation of forming the trenches 304 includes removing a portion of thedevice layer 302 and a portion of the substrate 300 which underlies theportion of the device layer 302, such that each of the trenches 304extends from the device layer 302 to the substrate 300. In someexemplary examples, the operation of forming the trenches 304 isperformed by using a photolithograph process and an etching process. Forexample, the etching process may be a dry etching process or a wetetching process.

As shown in FIG. 3C, an anti-reflective coating layer 308 is formed toconformally cover the device layer 302, the substrate 300 and thetrenches 304. The operation of forming the anti-reflective coating layer308 may be performed by using a deposition technique, such as a chemicalvapor deposition (CVD) technique or a physical vapor deposition (PVD)technique. The anti-reflective coating layer 308 may be formed fromsilicon oxide.

As shown in FIG. 3D, various discrete reflective structures 310 areformed on the anti-reflective coating layer 308 in the trenches 304respectively by using a deposition technique, such as a chemical vapordeposition technique, a physical vapor deposition technique or aplasma-enhanced chemical vapor deposition (PECVD) technique. Theoperation of forming the reflective structures 310 includes forming thereflective structures 310 filling the trenches 304 respectively. Thereflective structures 310 may be formed from metal or dielectricmaterial. In some exemplary examples, the reflective structures 310 areformed from the dielectric material, and each of the reflectivestructures 310 is formed to be a deep trench isolation structure. Forexample, each of the reflective structures 310 may be formed to have aheight ranging from about 0.1 micrometer to about 2.5 micrometer. Thetrenches 304 are only formed in the border areas 306, such that thereflective structures 310 formed in the trenches 304 are located in theborder areas 306.

In some examples, as shown in FIG. 3E, a buffer layer 312 may beoptionally formed on and covering the anti-reflective coating layer 308and the reflective structures 310. The operation of forming the bufferlayer 312 may be performed by using a deposition technique, such as achemical vapor deposition technique. For example, the buffer layer 312may be formed from a dielectric layer, such as silicon dioxide.

Referring to FIG. 3F and FIG. 3G simultaneously, a metal grid structure320 is formed on the buffer layer 312 over the anti-reflective coatinglayer 308. In some examples, the operation of forming the metal gridstructure 320 includes forming a metal layer 314 to cover the bufferlayer 312 over the anti-reflective coating layer 308 and the reflectivestructures 310, as shown in FIG. 3F. The metal layer 314 is formed frommetal or metal alloy, such as tungsten or aluminum-copper alloy. Themetal layer 314 and the reflective structures 310 may be formed from thesame material, or may be formed from different materials. The metallayer 314 may be formed by using, for example, a chemical vapordeposition technique or a physical vapor deposition technique.

Referring to FIG. 3F and FIG. 3G again, various cavities 318 are formedin the metal layer 314, so as to complete a metal grid structure 320,which is located on the buffer layer 312 overlying the anti-reflectivecoating layer 308. For example, the operation of forming the cavities318 may be performed by using a photolithography process and an etchingprocess. The operation of forming the cavities 318 includes removing aportion of the metal layer 314 to form various discrete metal blockingstructures 322. The cavities 318 pass through the metal layer 314 toexpose portions of the buffer layer 312. In some examples, as shown inFIG. 3G, each cavity 318 is formed to have a cross section in a shape oftrapezoid or rectangle. As shown in FIG. 3G, the metal blockingstructures 322 are only formed in intersection areas 316 while thereflective structures 310 are only formed in the border areas 306, suchthat the metal blocking structures 322 and the reflective structures 310are staggered and define various pixel portions 323 (such as the pixelportions 108 shown in FIG. 1A and FIG. 1B) over the substrate 300. Eachof the pixel portions 323 includes various intersection areas 316,various border areas 306 and a central area (not shown), in which eachborder area 306 is located between any two adjacent ones of theintersection areas 316, and the central area surrounded by theintersection areas 316 and the border areas 306, such as the pixelportions 108 shown in FIG. 1A and FIG. 1B.

As shown in FIG. 3H, a passivation layer 324 is formed to conformallycover the metal blocking structures 322 of the metal grid structure 320and the portions of the buffer layer 312 exposed by the cavities 318.The metal blocking structures 322 overly the anti-reflective coatinglayer 308, and the portions of the buffer layer 312 exposed by thecavities 318 overly the reflective structures 310, such that thepassivation layer 324 covers the anti-reflective coating layer 308 andthe reflective structures 310. The operation of forming the passivationlayer 324 may be performed by using, for example, a chemical vapordeposition technique or a physical vapor deposition technique. In someexamples, the passivation layer 324 is formed from silicon oxide,silicon nitride or silicon oxynitride.

As shown in FIG. 3I, various color filters 326 are formed on thepassivation layer 324 and respectively filling the cavities 318. Thecolor filters 326 are respectively formed in the pixel portions 323. Thecolor filters 326 may be arranged sequentially. In some exemplaryexamples, the color filters 326 are formed to include red color filters,blue color filters and green color filters. In some examples, theoperation of forming the color filters 326 is performed to form each ofthe color filters 326 having a top surface 328, in which the topsurfaces 328 are higher than a top 330 of the passivation layer 324.Referring to FIG. 3I again, various micro lenses 332 may be optionallyformed to cover the top surfaces 328 of the color filters 326respectively, so as to complete a CMOS image sensor structure 334.

Referring to FIG. 4 with FIG. 3A through FIG. 3I, FIG. 4 is a flow chartof a method for manufacturing a CMOS image sensor structure inaccordance with various embodiments. The method begins at operation 400,where a substrate 300 is provided. At operation 402, a device layer 302is formed on the substrate 300, as shown in FIG. 3A. The operation offorming the device layer 302 may be performed using, for example, adeposition technique, an epitaxial technique or a bonding technique.

At operation 404, as shown in FIG. 3B, various trenches 304 are formedin the device layer 302 and the substrate 300 by using a photolithographprocess and an etching process. For example, the etching process may bea dry etching process or a wet etching process. In the embodiment, thetrenches 304 are only formed in border areas 306. In some examples, theoperation of forming the trenches 304 is performed to form various deeptrenches. The operation of forming the trenches 304 includes removing aportion of the device layer 302 and a portion of the substrate 300 whichunderlies the portion of the device layer 302, such that each of thetrenches 304 extends from the device layer 302 to the substrate 300.

At operation 406, as shown in FIG. 3C, an anti-reflective coating layer308 is formed to conformally cover the device layer 302, the substrate300 and the trenches 304 by using a deposition technique, such as achemical vapor deposition technique or a physical vapor depositiontechnique.

At operation 408, as shown in FIG. 3D, various discrete reflectivestructures 310 are formed on the anti-reflective coating layer 308 inthe trenches 304 respectively by using a deposition technique, such as achemical vapor deposition technique, a physical vapor depositiontechnique or a plasma-enhanced chemical vapor deposition technique. Theoperation of forming the reflective structures 310 includes forming thereflective structures 310 filling the trenches 304 respectively. In someexemplary examples, each of the reflective structures 310 is formed tobe a deep trench isolation structure. For example, each of thereflective structures 510 may be formed to have a height ranging fromabout 0.1 micrometer to about 2.5 micrometer. The trenches 304 are onlyformed in the border areas 306, such that the reflective structures 310formed in the trenches 304 are located in the border areas 306. As shownin FIG. 3E, a buffer layer 312 may be optionally formed on and coveringthe anti-reflective coating layer 308 and the reflective structures 310by using a deposition technique, such as a chemical vapor depositiontechnique.

At operation 410, referring to FIG. 3F and FIG. 3G simultaneously, ametal grid structure 320 is formed on the buffer layer 312 over theanti-reflective coating layer 308. In some examples, the operation offorming the metal grid structure 320 includes forming a metal layer 314to cover the buffer layer 312 over the anti-reflective coating layer 308and the reflective structures 310, as shown in FIG. 3F. The metal layer314 may be formed by using, for example, a chemical vapor depositiontechnique or a physical vapor deposition technique.

Referring to FIG. 3F and FIG. 3G again, various cavities 318 are formedin the metal layer 314 by using a photolithography process and anetching process, so as to complete a metal grid structure 320 on thebuffer layer 312. The operation of forming the cavities 318 includesremoving a portion of the metal layer 314 to form various discrete metalblocking structures 322. The cavities 318 pass through the metal layer314 to expose portions of the buffer layer 312. As shown in FIG. 3G, themetal blocking structures 322 are only formed in intersection areas 316while the reflective structures 310 are only formed in the border areas306, such that the metal blocking structures 322 and the reflectivestructures 310 are staggered and define various pixel portions 323 (suchas the pixel portions 108 shown in FIG. 1A and FIG. 1B) over thesubstrate 300. Each of the pixel portions 323 includes variousintersection areas 316, various border areas 306 and a central area (notshown), in which each border area 306 is located between any twoadjacent ones of the intersection areas 316, and the central areasurrounded by the intersection areas 316 and the border areas 306, suchas the pixel portions 108 shown in FIG. 1A and FIG. 1B.

At operation 412, as shown in FIG. 3H, a passivation layer 324 is formedto conformally cover the metal blocking structures 322 and the portionsof the buffer layer 312 exposed by the cavities 318. The operation offorming the passivation layer 324 may be performed by using, forexample, a chemical vapor deposition technique or a physical vapordeposition technique.

At operation 414, as shown in FIG. 3I, various color filters 326 areformed on the passivation layer 324 and respectively filling thecavities 318. The color filters 326 are respectively formed in the pixelportions 323. In some exemplary examples, the color filters 326 areformed to include red color filters, blue color filters and green colorfilters. In some examples, the operation of forming the color filters326 is performed to form each of the color filters 326 having a topsurface 328, in which the top surfaces 328 are higher than a top 330 ofthe passivation layer 324. Referring to FIG. 3I again, various microlenses 332 may be optionally formed to cover the top surfaces 328 of thecolor filters 326 respectively, so as to complete a CMOS image sensorstructure 334.

FIG. 5A through FIG. 5I are schematic cross-sectional views ofintermediate stages showing a method for manufacturing a CMOS imagesensor structure in accordance with various embodiments. As shown inFIG. 5A, a substrate 500 is provided. The substrate 500 is asemiconductor substrate, and may be composed of a single-crystallinesemiconductor material or a compound semiconductor material. Forexample, silicon, germanium or glass may be used as a material of thesubstrate 500.

Referring to FIG. 5A again, a device layer 502 is formed on thesubstrate 500 by using, for example, a deposition technique, anepitaxial technique or a bonding technique. In some examples, theoperation of forming the device layer 502 includes forming the devicelayer 502 from silicon. For example, the device layer 502 may be formedfrom epitaxial silicon.

As shown in FIG. 5B, various trenches 504 are formed in the device layer502 and the substrate 500. In the embodiment, the trenches 504 are onlyformed in intersection areas 506. In some examples, the operation offorming the trenches 504 is performed to form various deep trenches. Theoperation of forming the trenches 504 includes removing a portion of thedevice layer 502 and a portion of the substrate 500 which underlies theportion of the device layer 502, such that each of the trenches 504extends from the device layer 502 to the substrate 500. In someexemplary examples, the operation of forming the trenches 504 isperformed by using a photolithograph process and an etching process. Forexample, the etching process may be a dry etching process or a wetetching process.

As shown in FIG. 5C, an anti-reflective coating layer 508 is formed toconformally cover the device layer 502, the substrate 500 and thetrenches 504. The operation of forming the anti-reflective coating layer508 may be performed by using a deposition technique, such as a chemicalvapor deposition technique or a physical vapor deposition technique. Theanti-reflective coating layer 508 may be formed from silicon oxide.

As shown in FIG. 5D, various discrete reflective structures 510 areformed on the anti-reflective coating layer 508 in the trenches 504respectively by using a deposition technique, such as a chemical vapordeposition technique, a physical vapor deposition technique or aplasma-enhanced chemical vapor deposition technique. The operation offorming the reflective structures 510 includes forming the reflectivestructures 510 filling the trenches 504 respectively. The reflectivestructures 510 may be formed from metal or dielectric material. In someexemplary examples, the reflective structures 510 are formed from thedielectric material, and each of the reflective structures 510 is formedto be a deep trench isolation structure. For example, each of thereflective structures 510 may be formed to have a height ranging fromabout 0.1 micrometer to about 2.5 micrometer. The trenches 504 are onlyformed in the intersection areas 506, such that the reflectivestructures 510 formed in the trenches 504 are located in theintersection areas 506.

In some examples, as shown in FIG. 5E, a buffer layer 512 may beoptionally formed on and covering the anti-reflective coating layer 508and the reflective structures 510. The operation of forming the bufferlayer 512 may be performed by using a deposition technique, such as achemical vapor deposition technique. For example, the buffer layer 512may be formed from a dielectric layer, such as silicon dioxide.

Referring to FIG. 5F and FIG. 5G simultaneously, a metal grid structure520 is formed on the buffer layer 512 over the anti-reflective coatinglayer 508. In some examples, the operation of forming the metal gridstructure 520 includes forming a metal layer 514 to cover the bufferlayer 512 over the anti-reflective coating layer 508 and the reflectivestructures 510, as shown in FIG. 5F. The metal layer 514 is formed frommetal or metal alloy, such as tungsten or aluminum-copper alloy. Themetal layer 514 and the reflective structures 510 may be formed from thesame material, or may be formed from different materials. The metallayer 514 may be formed by using, for example, a chemical vapordeposition technique or a physical vapor deposition technique.

Referring to FIG. 5F and FIG. 5G again, various cavities 518 are formedin the metal layer 514, so as to complete a metal grid structure 520,which is located on the buffer layer 512 overlying the anti-reflectivecoating layer 508. For example, the operation of forming the cavities518 may be performed by using a photolithography process and an etchingprocess. The operation of forming the cavities 518 includes removing aportion of the metal layer 514 to form various discrete metal blockingstructures 522. The cavities 518 pass through the metal layer 514 toexpose portions of the buffer layer 512. In some examples, as shown inFIG. 5G, each cavity 518 is formed to have a cross section in a shape oftrapezoid or rectangle. As shown in FIG. 5G, the metal blockingstructures 522 are only formed in border areas 516 while the reflectivestructures 510 are only formed in the intersection areas 506, such thatthe metal blocking structures 522 and the reflective structures 510 arestaggered and define various pixel portions 523 (such as the pixelportions 208 shown in FIG. 2A and FIG. 2B) over the substrate 500. Eachof the pixel portions 523 includes various intersection areas 506,various border areas 516 and a central area (not shown), in which eachborder area 516 is located between any two adjacent ones of theintersection areas 506, and the central area surrounded by theintersection areas 506 and the border areas 516, such as the pixelportions 208 shown in FIG. 2A and FIG. 2B.

As shown in FIG. 5H, a passivation layer 524 is formed to conformallycover the metal blocking structures 522 of the metal grid structure 520and the portions of the buffer layer 512 exposed by the cavities 518.The metal blocking structures 522 overly the anti-reflective coatinglayer 508, and the portions of the buffer layer 512 exposed by thecavities 518 overly the reflective structures 510, such that thepassivation layer 524 covers the anti-reflective coating layer 508 andthe reflective structures 510. The operation of forming the passivationlayer 524 may be performed by using, for example, a chemical vapordeposition technique or a physical vapor deposition technique. In someexamples, the passivation layer 524 is formed from silicon oxide,silicon nitride or silicon oxynitride.

As shown in FIG. 5I, various color filters 526 are formed on thepassivation layer 524 and respectively filling the cavities 518. Thecolor filters 526 are respectively formed in the pixel portions 523. Thecolor filters 526 may be arranged sequentially. In some exemplaryexamples, the color filters 526 are formed to include red color filters,blue color filters and green color filters. In some examples, theoperation of forming the color filters 526 is performed to form each ofthe color filters 526 having a top surface 528, in which the topsurfaces 528 are higher than a top 530 of the passivation layer 524.Referring to FIG. 5I again, various micro lenses 532 may be optionallyformed to cover the top surfaces 528 of the color filters 526respectively, so as to complete a CMOS image sensor structure 534.

Referring to FIG. 6 with FIG. 5A through FIG. 5I, FIG. 6 is a flow chartof a method for manufacturing a CMOS image sensor structure inaccordance with various embodiments. The method begins at operation 600,where a substrate 500 is provided. At operation 502, a device layer 502is formed on the substrate 500, as shown in FIG. 5A. The operation offorming the device layer 502 may be performed using, for example, adeposition technique, an epitaxial technique or a bonding technique.

At operation 604, as shown in FIG. 5B, various trenches 504 are formedin the device layer 502 and the substrate 500 by using a photolithographprocess and an etching process. For example, the etching process may bea dry etching process or a wet etching process. In the embodiment, thetrenches 504 are only formed in intersection areas 506. In someexamples, the operation of forming the trenches 504 is performed to formvarious deep trenches. The operation of forming the trenches 504includes removing a portion of the device layer 502 and a portion of thesubstrate 500 which underlies the portion of the device layer 502, suchthat each of the trenches 504 extends from the device layer 502 to thesubstrate 500.

At operation 606, as shown in FIG. 5C, an anti-reflective coating layer508 is formed to conformally cover the device layer 502, the substrate500 and the trenches 504 by using a deposition technique, such as achemical vapor deposition technique or a physical vapor depositiontechnique.

At operation 608, as shown in FIG. 5D, various discrete reflectivestructures 510 are formed on the anti-reflective coating layer 508 inthe trenches 504 respectively by using a deposition technique, such as achemical vapor deposition technique, a physical vapor depositiontechnique or a plasma-enhanced chemical vapor deposition technique. Theoperation of forming the reflective structures 510 includes forming thereflective structures 510 filling the trenches 504 respectively. In someexemplary examples, each of the reflective structures 510 is formed tobe a deep trench isolation structure. For example, each of thereflective structures 510 may be formed to have a height ranging fromabout 0.1 micrometer to about 2.5 micrometer. The trenches 504 are onlyformed in the intersection areas 506, such that the reflectivestructures 510 formed in the trenches 504 are located in theintersection areas 506. As shown in FIG. 5E, a buffer layer 512 may beoptionally formed on and covering the anti-reflective coating layer 508and the reflective structures 510 by using a deposition technique, suchas a chemical vapor deposition technique.

At operation 610, referring to FIG. 5F and FIG. 5G simultaneously, ametal grid structure 520 is formed on the buffer layer 512 over theanti-reflective coating layer 508. In some examples, the operation offorming the metal grid structure 520 includes forming a metal layer 514to cover the buffer layer 512 over the anti-reflective coating layer 508and the reflective structures 510, as shown in FIG. 5F. The metal layer514 may be formed by using, for example, a chemical vapor depositiontechnique or a physical vapor deposition technique.

Referring to FIG. 5F and FIG. 5G again, various cavities 518 are formedin the metal layer 514 by using a photolithography process and anetching process, so as to complete a metal grid structure 520 on thebuffer layer 512. The operation of forming the cavities 518 includesremoving a portion of the metal layer 514 to form various discrete metalblocking structures 522. The cavities 518 pass through the metal layer514 to expose portions of the buffer layer 512. As shown in FIG. 5G, themetal blocking structures 522 are only formed in border areas 516 whilethe reflective structures 510 are only formed in the intersection areas506, such that the metal blocking structures 522 and the reflectivestructures 510 are staggered and define various pixel portions 523 (suchas the pixel portions 208 shown in FIG. 2A and FIG. 2B) over thesubstrate 500. Each of the pixel portions 523 includes variousintersection areas 506, various border areas 516 and a central area (notshown), in which each border area 516 is located between any twoadjacent ones of the intersection areas 506, and the central areasurrounded by the intersection areas 506 and the border areas 516, suchas the pixel portions 208 shown in FIG. 2A and FIG. 2B.

At operation 612, as shown in FIG. 5H, a passivation layer 524 is formedto conformally cover the metal blocking structures 522 and the portionsof the buffer layer 512 exposed by the cavities 518. The operation offorming the passivation layer 524 may be performed by using, forexample, a chemical vapor deposition technique or a physical vapordeposition technique.

At operation 614, as shown in FIG. 5I, various color filters 526 areformed on the passivation layer 524 and respectively filling thecavities 518. The color filters 526 are respectively formed in the pixelportions 523. In some exemplary examples, the color filters 526 areformed to include red color filters, blue color filters and green colorfilters. In some examples, the operation of forming the color filters526 is performed to form each of the color filters 526 having a topsurface 528, in which the top surfaces 528 are higher than a top 530 ofthe passivation layer 524. Referring to FIG. 5I again, various microlenses 532 may be optionally formed to cover the top surfaces 528 of thecolor filters 526 respectively, so as to complete a CMOS image sensorstructure 534.

In accordance with an embodiment, the present disclosure discloses aCMOS image sensor structure. The CMOS image sensor structure includes asubstrate and various pixel portions, in which the pixel portions aredisposed adjacent to each other on the substrate. Each of the pixelportions includes various intersection areas, various the border areaseach of which is located between any two adjacent ones of theintersection areas, and a central area surrounded by the intersectionareas and the border areas. Each of the pixel portions includes a devicelayer, an anti-reflective coating layer, various discrete reflectivestructures, various discrete metal blocking structures, a passivationlayer and a color filter. The device layer is disposed in theintersection areas, the border areas and the central area on thesubstrate. Various trenches are formed in the device layer and thesubstrate corresponding to the border areas respectively. Theanti-reflective coating layer conformally covers the device layer, thesubstrate and the trenches. The reflective structures are disposed onthe anti-reflective coating layer in the trenches respectively. Themetal blocking structures overly the anti-reflective coating layer inthe intersection areas respectively. The passivation layer conformallycovers the metal blocking structures, the anti-reflective coating layerand the reflective structures. The color filter is disposed on thepassivation layer in the intersection areas, the border areas and thecentral area.

In accordance with another embodiment, the present disclosure disclosesa CMOS image sensor structure. The CMOS image sensor structure asubstrate and various pixel portions, in which the pixel portions aredisposed adjacent to each other on the substrate. Each of the pixelportions includes various intersection areas, various the border areaseach of which is located between any two adjacent ones of theintersection areas, and a central area surrounded by the intersectionareas and the border areas. Each of the pixel portions includes a devicelayer, an anti-reflective coating layer, various discrete reflectivestructures, various discrete metal blocking structures, a passivationlayer and a color filter. The device layer is disposed in theintersection areas, the border areas and the central area on thesubstrate. Various trenches are formed in the device layer and thesubstrate corresponding to the intersection areas respectively. Theanti-reflective coating layer conformally covers the device layer, thesubstrate and the trenches. The reflective structures are disposed onthe anti-reflective coating layer in the trenches respectively. Themetal blocking structures overly the anti-reflective coating layer inthe border areas respectively. The passivation layer conformally coversthe metal blocking structures, the anti-reflective coating layer and thereflective structures. The color filter is disposed on the passivationlayer in the intersection areas, the border areas and the central area.

In accordance with yet another embodiment, the present disclosurediscloses a method for manufacturing a CMOS image sensor structure. Inthis method, a substrate is provided. A device layer is formed on thesubstrate. Various trenches are formed to extend from the device layerto the substrate. An anti-reflective coating layer is formed toconformally cover the device layer, the substrate and the trenches.Various discrete reflective structures are formed on the anti-reflectivecoating layer in the trenches respectively. A metal grid structure isformed over the anti-reflective coating layer. The metal grid structureis formed to include various discrete metal blocking structures, and themetal blocking structures and the reflective structures are staggeredand define various pixel portions over the substrate. A passivationlayer is formed to conformally cover the metal blocking structures, theanti-reflective coating layer and the reflective structures. Variouscolor filters are formed on the passivation layer in the pixel portionsrespectively.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A CMOS image sensor structure, comprising: asubstrate; and a plurality of pixel portions disposed adjacent to eachother on the substrate, wherein each of the pixel portions comprises aplurality of intersection areas, a plurality of border areas each ofwhich is located between any two adjacent ones of the intersectionareas, and a central area surrounded by the intersection areas and theborder areas, wherein each of the pixel portions comprises: a devicelayer disposed in the intersection areas, the border areas and thecentral area on the substrate, wherein a plurality of trenches areformed in the device layer and the substrate corresponding to theintersection areas respectively; an anti-reflective coating layerconformally covering the device layer, the substrate and the trenches; aplurality of discrete reflective structures disposed on theanti-reflective coating layer in the trenches respectively; a pluralityof discrete metal blocking structures overlying the anti-reflectivecoating layer in the border areas respectively, wherein the metalblocking structures and the reflective structures are staggered andsurround the central area; a passivation layer conformally covering themetal blocking structures, the anti-reflective coating layer and thereflective structures; and a color filter disposed on the passivationlayer in the intersection areas, the border areas and the central area.2. The CMOS image sensor structure of claim 1, wherein each of thereflective structures is a deep trench isolation structure.
 3. The CMOSimage sensor structure of claim 1, wherein each of the reflectivestructures has a height ranging substantially from 0.1 micrometer to 2.5micrometer.
 4. The CMOS image sensor structure of claim 1, wherein thereflective structures are formed from metal.
 5. The CMOS image sensorstructure of claim 1, wherein the metal blocking structures are formedfrom tungsten or an aluminum-copper alloy.
 6. The CMOS image sensorstructure of claim 1, further comprising a buffer layer disposed betweenthe anti-reflective coating layer and the passivation layer.
 7. The CMOSimage sensor structure of claim 1, wherein each of the pixel portionsfurther comprises a micro lens covering a top surface of the colorfilter.
 8. The CMOS image sensor structure of claim 1, wherein each ofthe reflective structures has a top surface which is elevated at thesame level with a top of the anti-reflective coating layer.
 9. An imagesensor comprising: a plurality of pixel portions over a substrate; aplurality of reflective structures, each of which is associated with arespective one of the pixel portions, wherein the reflective structuresare discrete and at least one of the reflective structures has a shapeof a crisscross; and a plurality of metal blocking structures over thereflective structures, wherein the reflective structures are misalignedwith the metal blocking structures.
 10. The image sensor of claim 9,wherein each of the reflective structures is at a corner of a respectiveone of the pixel portions.
 11. The image sensor of claim 9, wherein eachof the metal blocking structures is between adjacent corners of arespective one of the pixel portions.
 12. The image sensor of claim 9,wherein the metal blocking structures are discrete and the reflectivestructures and the metal blocking structures complement each other toform a grid.
 13. An image sensor comprising: a plurality of pixelportions over a substrate; a plurality of reflective structures, each ofwhich is associated with a respective one of the pixel portions; and aplurality of metal blocking structures over the reflective structures,wherein each of the metal blocking structures includes a plurality ofdiscrete portions in a top view that surround a central area of arespective one of the pixel portions and the reflective structures aremisaligned with the metal blocking structures.
 14. The image sensor ofclaim 13, wherein each of the metal blocking structures further includesa plurality of second discrete portions that surround a corner of arespective one of the pixel portions.
 15. The image sensor of claim 13,wherein a first pair of the discrete portions of one of the metalblocking structures are aligned with each other in a first direction.16. The image sensor of claim 15, wherein a second pair of the discreteportions of one of the metal blocking structures are aligned with eachother in a second direction transverse to the first direction.
 17. Theimage sensor of claim 13, wherein each of the discrete portions of oneof the metal blocking structures is between adjacent corners of one ofthe pixel portions.
 18. The image sensor of claim 13, wherein thereflective structures are discrete and each of the reflective structuresis at a corner of a respective one of the pixel portions.
 19. The imagesensor of claim 13, wherein the reflective structures are discrete andat least one of the reflective structures has a shape of a crisscross.20. The image sensor of claim 13, wherein one of the reflectivestructures and one of the metal blocking structures complement eachother to form a shape of a crisscross.